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Mesa Electronics 7i76 Step/Direction + I/O Daughter Card
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Revision as of 10:59, 20 October 2022
362 bytes added
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10:59, 20 October 2022
added idle voltage levels
Line 14:
Line 14:
* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=14 Pages 14-15] (8-9 in the PDF) show the TB5 field I/O pinout
* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=14 Pages 14-15] (8-9 in the PDF) show the TB5 field I/O pinout
* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=16 Page 16] (10 in the PDF) shows the TB1 field power pinout
* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=16 Page 16] (10 in the PDF) shows the TB1 field power pinout
+
+
Give that all of the FPGA pins are being driven to +5V (high), the 7i76 has the following output levels with respect to digital ground:
+
+
{| class="wikitable"
+
! TBx Pin
+
! Voltage
+
|-
+
| STEP/DIRx+
+
| +5V (high)
+
|-
+
| STEP/DIRx-
+
| 0V (low)
+
|-
+
| RS-422 TX+
+
| 0V (low)
+
|-
+
| RS-422 TX-
+
| +5V (high)
+
|-
+
| RS-422 RX+
+
| +2.5V (invalid)
+
|-
+
| RS-422 RX-
+
| +2.5V (invalid)
+
|}
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