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added idle voltage levels
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* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=14 Pages 14-15] (8-9 in the PDF) show the TB5 field I/O pinout
 
* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=14 Pages 14-15] (8-9 in the PDF) show the TB5 field I/O pinout
 
* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=16 Page 16] (10 in the PDF) shows the TB1 field power pinout
 
* [http://www.mesanet.com/pdf/parallel/7i76man.pdf#page=16 Page 16] (10 in the PDF) shows the TB1 field power pinout
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 +
Give that all of the FPGA pins are being driven to +5V (high), the 7i76 has the following output levels with respect to digital ground:
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{| class="wikitable"
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! TBx Pin
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! Voltage
 +
|-
 +
| STEP/DIRx+
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| +5V (high)
 +
|-
 +
| STEP/DIRx-
 +
| 0V (low)
 +
|-
 +
| RS-422 TX+
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| 0V (low)
 +
|-
 +
| RS-422 TX-
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| +5V (high)
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|-
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| RS-422 RX+
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| +2.5V (invalid)
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|-
 +
| RS-422 RX-
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| +2.5V (invalid)
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|}
    
== Dimensions ==
 
== Dimensions ==
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[http://store.mesanet.com/index.php?route=product/product&product_id=119 7i76 | Mesa Web Store]
 
[http://store.mesanet.com/index.php?route=product/product&product_id=119 7i76 | Mesa Web Store]
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[http://store.mesanet.com/index.php?route=product/product&product_id=322 7i76 | Mesa Web Store]
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[http://store.mesanet.com/index.php?route=product/product&product_id=322 7i76D | Mesa Web Store]

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